Semiconductor chip, chip-on-chip structure device, and assembling method thereof

ABSTRACT

A semiconductor chip ( 3 ) to be positioned with a front face thereof downward for formation of a chip-on-chip structure has electrode marks ( 35 ) provided on a back face ( 34 ) thereof. The electrode marks ( 35 ) are respectively provided in association with a plurality of electrodes ( 33 ) provided on the front face ( 31 ) of the semiconductor chip in the same arrangement as the arrangement of the electrodes ( 33 ). The arrangement of the electrode marks ( 35 ) represents the arrangement of the electrodes ( 33 ) on the front face ( 31 ) when viewed from the side of the back face ( 34 ) of the semiconductor chip  3 . Therefore, the semiconductor chip ( 3 ) can easily be positioned with the front face downward on the basis of the electrode marks ( 35 ).

[0001] This application is based on application Nos. 11-30478, 11-30479,11-30480, 11-38794 and 11-47078 filed in Japan, the contents of whichare incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to semiconductor chips for aso-called chip-on-chip structure which includes a plurality ofsemiconductor chips bonded in a double-stacked relation, chip-on-chipsemiconductor devices, and chip-on-chip mounting methods.

[0004] 2. Description of Related Art

[0005] For size reduction and higher integration of semiconductordevices, a proposal has been made to shift the design concept from aconventional two-dimensional structure to a three-dimensional structure.

[0006] However, production of semiconductor devices of three-dimensionalstructure through a continuous process often encounters difficultiessuch as a lower yield.

[0007] The inventors of the present invention have been conductingstudies on practical applications of a semiconductor device of so-calledchip-on-chip structure which includes a plurality of semiconductor chipsbonded to one another in a face-to-face double-stacked relation.

[0008] Where semiconductor chips are bonded to each other in a stackedrelation, for example, where a relatively small secondary chip is laidon the front face of a relatively large primary chip, the secondary chipcan easily be positioned in alignment with the primary chip with thefront face thereof upward and with the back face thereof opposed to thefront face of the primary chip.

[0009] However, if an attempt is made to stack the primary chip and thesecondary chip in a face-to-face relation, there is a difficulty inaligning these semiconductor chips with each other. This is because theorientation of a semiconductor chip, the arrangement of electrodes onthe front face of the semiconductor chip and the like cannot be checkedfrom the back side thereof.

[0010] Particularly, the electrodes are not always arranged in apredetermined positional relationship with the profile of thesemiconductor chip, but the positional relationship between theelectrode arrangement and the profile varies depending on dicingconditions under which a semiconductor wafer is diced into semiconductorchips. Therefore, it is difficult to align or position the semiconductorchips with respect to each other by viewing either of the semiconductorchips from the back side thereof.

[0011] Even if the primary and secondary chips have substantially thesame size, the alignment of the semiconductor chips for bonding thereofis difficult.

SUMMARY OF THE INVENTION

[0012] In view of the foregoing, it is a principal object of the presentinvention to provide a chip-on-chip structure which includes a pluralityof semiconductor chips bonded to one another in a face-to-face stackedrelation for practical applications.

[0013] It is another object of the invention to provide a semiconductorchip for chip-on-chip mounting to provide the chip-on-chip structure forpractical applications.

[0014] It is further another object of the invention to provide achip-on-chip semiconductor device and a mounting method therefor.

[0015] A feature of the present invention is generally to provide markssuch as an electrode mark, a back mark and an alignment mark on the backface of a semiconductor chip for recognition of the orientation of thesemiconductor chip and the electrode arrangement on the semiconductorchip.

[0016] More specifically, in accordance with an inventive aspect ofclaim 1, there is provided a semiconductor chip for a chip-on-chipstructure in which a plurality of semiconductor chips are bonded to oneanother in a stacked relation with electrode-carrying front facesthereof opposed to each other, the semiconductor chip comprising anelectrode mark provided on a back face thereof in association with anelectrode provided on a front face thereof.

[0017] In accordance with an inventive aspect of claim 2, thesemiconductor chip for the chip-on-chip structure according to claim 1is characterized in that a plurality of electrodes are provided in apredetermined arrangement on the front face of the semiconductor chip,and a plurality of electrode marks are provided on the back face of thesemiconductor chip in association with the respective electrodes in thesame arrangement as the electrode arrangement.

[0018] In accordance with an inventive aspect of claim 3, thesemiconductor chip for the chip-on-chip structure according to claim 1is characterized in that a plurality of electrodes are provided in apredetermined arrangement on the front face of the semiconductor chip,and electrode marks are provided on the back face of the semiconductorchip in association with predetermined ones of the plurality ofelectrodes.

[0019] In accordance with an inventive aspect of claim 4, there isprovided a chip-on-chip semiconductor device which comprises a pluralityof semiconductor chips bonded to one another in a stacked relation withelectrode-carrying front faces thereof opposed to each other viaelectrodes provided on the opposed front faces, wherein electrode marksare provided on a back face of at least one of the stacked semiconductorchips in association with the electrodes on the front face of the onesemiconductor chip.

[0020] In accordance with an inventive aspect of claim 5, there isprovided a chip-on-chip mounting method for stacking first and secondsemiconductor chips each having electrodes provided on a front facethereof so that the electrodes on the first semiconductor chip arebonded to the electrodes on the second semiconductor chip, the methodcomprising the steps of: placing the first semiconductor chip with thefront face thereof upward; and positioning the second semiconductor chipwith respect to the first semiconductor chip on the basis of electrodemarks provided on a back face of the second semiconductor chip inassociation with the electrodes provided on the front face of the secondsemiconductor chip to mount the second semiconductor chip on the firstsemiconductor chip with the front face of the second semiconductor chipfacing downward as opposed to the front face of the first semiconductorchip.

[0021] With the arrangements according to claims 1 to 3, when thechip-on-chip structure is assembled with the front face of thesemiconductor chip downward, the positioning of the semiconductor chipcan be achieved on the basis of the electrode marks provided on the backface of the semiconductor chip. The electrode marks on the back face ofthe semiconductor chip are located in association with the electrodes onthe front face of the semiconductor chip. The electrode marks providedin association with the electrodes may each be defined, for example, asa mark which surrounds an intersection between the back face and aphantom vertical line extending vertically through the semiconductorchip from an electrode. In other words, the electrode marks are eachdefined as a mark of an electrode as seen through the semiconductor chipfrom the back side thereof.

[0022] Therefore, with the electrode marks, the positions of theelectrodes can be checked from the back side of the semiconductor chip,so that the semiconductor chip can properly be positioned with its facedown in a desired position on another semiconductor chip to be bondedthereto. As a result, the chip-on-chip structure can be produced withalmost no offset between the opposed electrodes. Since the positioningof the semiconductor chips is easy, the time required for assembling thechip-on-chip structure can be reduced.

[0023] Although the electrode marks are provided in association with therespective electrodes in accordance with claim 2, the electrode marksmay be provided in association with specific ones of the electrodes forthe purpose of the proper positioning of the semiconductor chip. Forexample, four electrode marks may be provided in association withelectrodes disposed in four corners of the semiconductor chip.

[0024] With the arrangement according to claim 4, the chip-on-chipsemiconductor device is provided in which the opposed electrodes arebonded to each other with a high level of precision, and the electrodepositions of the semiconductor device can be checked. Further, it caneasily be checked if the chip-on-chip semiconductor device is producedby employing any of the semiconductor chips according to claims 1 to 3.

[0025] With the arrangement according to claim 5, the chip-on-chipstructure can be assembled by utilizing the electrode marks. In otherwords, the chip-on-chip mounting method provides an assembling methodfor a chip-on-chip semiconductor device, which can be employed forpractical applications on actual production lines.

[0026] In accordance with an inventive aspect of claim 6, there isprovided a primary semiconductor chip serving as a base to be mountedwith a secondary semiconductor chip with a front face thereof bonded tothe secondary semiconductor chip, the primary semiconductor chipcomprising a mark provided on the front face thereof to be utilized as apositioning reference mark when the primary and secondary semiconductorchips are to be stacked.

[0027] In accordance with an inventive aspect of claim 7, the primarysemiconductor chip according to claim 6 is characterized in that aplurality of secondary semiconductor chips are to be mounted on thefront face of the primary semiconductor chip, and different positioningreference marks are provided on the front face of the primarysemiconductor chip in association with chip mounting positions in whichthe respective secondary semiconductor chips are to be mounted.

[0028] In accordance with an inventive aspect of claim 8, there isprovided a method for mounting a secondary semiconductor chip on a frontface of a primary semiconductor chip serving as a base, the methodcomprising the steps of: providing on the front face of the primarysemiconductor chip a mark which serves as a positioning reference markwhen the primary and secondary semiconductor chips are to be stacked;and positioning the secondary semiconductor chip on the front face ofthe primary semiconductor chip on the basis of the positioning referencemark.

[0029] With the arrangements according to claims 6 to 8, the secondarysemiconductor chip can be positioned with respect to the primarysemiconductor chip on the basis of the positioning reference markprovided on the front face of the primary semiconductor chip.

[0030] Where the secondary semiconductor chip is to be mounted on theprimary semiconductor chip, for example, with the use of mechanicalhands by determining positioning coordinates for the secondarysemiconductor chip on the basis of a profile-based positionalrelationship between the primary semiconductor chip and the secondarysemiconductor chip, the positioning control is difficult.

[0031] This is because electrodes arranged on front faces of thesemiconductor chips generally have a size on the order of 100 i and anallowable offset for the positioning of the semiconductor chips with theopposed electrodes of a size of 100 i aligned with each other issupposedly about ±5 to 10 i.

[0032] However, the positioning offset cannot be accommodated within theaforesaid allowable range where the positioning is based on thepositioning coordinates for the secondary semiconductor chip determinedon the basis of the positional relationship between the primarysemiconductor chip and the secondary semiconductor chip.

[0033] This is why the positioning of the secondary semiconductor chipis based on the positioning reference mark preliminarily provided on thefront face of the primary semiconductor chip in accordance with thepresent invention.

[0034] Thus, the secondary semiconductor chip can properly be positionedwith respect to the primary semiconductor chip with a positioning offsetwithin the aforesaid allowable range.

[0035] The positioning reference mark is not necessarily required tohave a great size but is preferably formed as a pin-point mark. This isbecause an image processing can more easily be performed on thepin-point mark for easy positioning of the secondary semiconductor chip.

[0036] The front face of the primary semiconductor chip is generallycovered with a passivation film, so that the mark can be provided in anydesired position.

[0037] With the arrangement according to claim 7, the differentpositioning reference marks for the respective secondary semiconductorchips to be mounted on the primary semiconductor chip are provided onthe front face of the primary semiconductor chip. This ensures easyimage processing for properly positioning the plurality of secondarysemiconductor chips in the predetermined positions on the primarysemiconductor chip.

[0038] In accordance with an inventive aspect of claim 9, there isprovided a semiconductor chip for a chip-on-chip structure in which aplurality of semiconductor chips are bonded to one another in aface-to-face stacked relation, the semiconductor chip comprising a backmark provided on a back face thereof for recognition of orientationthereof and electrode arrangement thereon.

[0039] The back mark preferably includes at least two back marks (claim10).

[0040] The back mark preferably includes a tally mark which is to bebrought into a predetermined positional relationship with a front markprovided on a front face of another semiconductor chip to be bonded tothe semiconductor chip in a stacked relation (claim 11).

[0041] With the provision of the back mark on the back face of thesemiconductor chip for the chip-on-chip structure, the semiconductorchip can be positioned with respect to the another semiconductor chip onthe basis of the back mark for formation of the chip-on-chip structure.

[0042] Particularly with the provision of two or more back marks, theorientations of the semiconductor chips to be stacked can correctly bechecked on the basis of the two or more back marks.

[0043] Where the back mark is provided on one of the semiconductor chipsand the front mark is provided on the other semiconductor chip, thesemiconductor chips to be stacked can more easily be positioned withrespect to each other by bringing the back mark and the front mark intoa predetermined positional relationship. This arrangement isparticularly effective where the two semiconductor chips to be stackedhave different sizes. Further, this arrangement is advantageous in thatproper positioning of the stacked semiconductor chips can be checked onthe basis of the positional relationship between the front mark and theback mark after the assembling of the chip-on-chip structure.

[0044] Thus, the back mark provided on the semiconductor chip allows thesemiconductor chip to be assembled into the chip-on-chip structure on aproduction line and the like. Since the positioning of the semiconductorchips with respect to each other can easily be achieved, the timerequired for assembling the chip-on-chip structure is effectivelyreduced.

[0045] In accordance with an inventive aspect of claim 12, thesemiconductor chip for the chip-on-chip structure is characterized inthat one of the plurality of semiconductor chips is a primary chip to bedisposed with the front face thereof upward, and another of theplurality of semiconductor chips is a secondary chip to be bonded ontothe primary chip with the front face thereof facing downward as opposedto the front face of the primary chip, and in that the back mark isprovided on the secondary chip.

[0046] With this arrangement, the secondary chip can easily bepositioned with respect to the primary chip when the primary andsecondary chips are to be bonded to each other in a stacked relation.Particularly, when the secondary chip is to be mounted on the primarychip preliminarily positioned, the positioning of the secondary chip caneasily be achieved.

[0047] In accordance with an inventive aspect of claim 13, thesemiconductor chip for the chip-on-chip structure is characterized inthat one of the plurality of semiconductor chips is a primary chip to bedisposed with the front face thereof upward, and another of theplurality of semiconductor chips is a secondary chip to be bonded ontothe primary chip with the front face thereof facing downward as opposedto the front face of the primary chip, and in that the back mark isprovided on the primary chip.

[0048] With this arrangement, the primary chip can easily be positionedwith respect to the secondary chip preliminarily positioned, or thepositioning of the secondary chip can be controlled on the basis of theback mark on the primary chip.

[0049] In accordance with an inventive aspect of claim 14, thesemiconductor chip for the chip-on-chip structure is characterized inthat one of the plurality of semiconductor chips is a primary chip to bedisposed with the front face thereof upward, and another of theplurality of semiconductor chips is a secondary chip to be bonded ontothe primary chip with the front face thereof facing downward as opposedto the front face of the primary chip, and in that the primary chip andthe secondary chip are each provided with the back mark.

[0050] This arrangement is advantageous not only where either theprimary chip or the secondary chip is preliminarily positioned but alsowhere the primary and secondary chips each held by a robot arm or thelike are positioned with respect to each other.

[0051] In accordance with an inventive aspect of claim 15, thesemiconductor chip for the chip-on-chip structure is characterized inthat one of the plurality of semiconductor chips is a primary chip to bedisposed with the front face thereof upward, and another of theplurality of semiconductor chips is a secondary chip to be bonded ontothe primary chip with the front face thereof facing downward as opposedto the front face of the primary chip, and in that the front mark isprovided on the front face of the primary chip and the back mark isprovided on the secondary chip in a predetermined positionalrelationship with the front mark on the primary chip.

[0052] This arrangement is advantageous in that the primary andsecondary chips can easily be positioned with respect to each other andwhether or not any offset occurs between the primary and secondary chipscan be checked after the chips are bonded to each other to form thechip-on-chip structure.

[0053] In accordance with an inventive aspect of claim 16, thesemiconductor chip for the chip-on-chip structure is characterized inthat a lead frame is fitted on the back face of the primary chip, andthe back mark is provided in a predetermined position on the lead frame.

[0054] With this arrangement, the fitting of the lead frame is easy, andthe formation of the chip-on-chip structure can be achieved by utilizingthe back mark on the lead frame in the same manner as the back mark onthe primary chip.

[0055] In accordance with an inventive aspect of claim 17, there isprovided a chip-on-chip semiconductor device, which comprises a firstsemiconductor chip disposed with a front face thereof upward, and asecond semiconductor chip bonded to the first semiconductor chip with afront face thereof facing downward as opposed to the front face of thefirst semiconductor chip, wherein a back mark is provided on a back faceof the second semiconductor chip so that the first and secondsemiconductor chips are positioned with respect to each other on thebasis of the back mark.

[0056] The back mark preferably includes at least two back marks (claim18).

[0057] In the chip-on-chip semiconductor device, a front mark may beprovided on the front face of the first semiconductor chip in apredetermined positional relationship with the back mark, and the firstand second semiconductor chips have been positioned with respect to eachother by bringing the back mark and the front mark into thepredetermined positional relationship (claim 19).

[0058] With this arrangement, the chip-on-chip semiconductor device canbe provided in which the first and second semiconductor chips areproperly positioned with respect to each other and bonded to each other.

[0059] Further, it can be checked whether or not the positioning of thesemiconductor chips with respect to each other is proper.

[0060] In accordance with an inventive aspect of claim 20, there isprovided a chip-on-chip mounting method, which comprises the steps of:placing a first semiconductor chip with a front face thereof upward; andpositioning a second semiconductor chip with respect to the firstsemiconductor chip on the basis of a back mark provided on a back faceof the second semiconductor chip to bond the first and secondsemiconductor chips to each other in a stacked relation with a frontface of the second semiconductor chip kept in a predetermined relationwith the front face of the first semiconductor chip.

[0061] In accordance with an inventive aspect of claim 21, there isprovided a chip-on-chip mounting method, which comprises the steps of:placing a first semiconductor chip having a back mark provided on a backface thereof with a front face thereof upward; and positioning a secondsemiconductor chip with respect to the first semiconductor chip on thebasis of the back mark provided on the first semiconductor chip to bondthe first and second semiconductor chips to each other in a stackedrelation with a front face of the second semiconductor chip kept in apredetermined relation with the front face of the first semiconductorchip.

[0062] In the aforesaid mounting methods, a front mark to be broughtinto a predetermined positional relationship with the back mark providedon the second or first semiconductor chip may be provided on the frontface of the first or second semiconductor chip not provided with theback mark, and the positioning may be achieved by bringing the back markand the front mark into the predetermined positional relationship (claim22).

[0063] This arrangement provides a practical assembling method for achip-on-chip semiconductor device. In other words, the assembling methodfor the chip-on-chip semiconductor device can be employed for practicalapplications on a production line or the like.

[0064] In these mounting methods, provision of two or more back marks isadvantageous in practical applications.

[0065] Further, it can be checked whether or not the positioning of thefirst and second semiconductor chips with respect to each other isproper in the chip-on-chip structure obtained through any of thesemethods.

[0066] In accordance with the present invention, the semiconductorchips, the semiconductor devices and the mounting methods are providedfor realizing the chip-on-chip structure.

[0067] In accordance with an inventive aspect of claim 23, there isprovided a semiconductor chip to be employed for assembling achip-on-chip structure in which semiconductor chips are bonded to eachother in a face-to-face stacked relation, the semiconductor chipcomprising an informational notation specific thereto provided on a backface thereof to be utilized at least when the chip-on-chip structure isassembled.

[0068] In accordance with an inventive aspect of claim 24, there isprovided a chip-on-chip semiconductor device which comprises a pluralityof semiconductor chips bonded to one another in a face-to-face stackedrelation, wherein at least one of the stacked semiconduct or chips hasan informational notation specific thereto provided on a back facethereof.

[0069] In the chip-on-chip semiconductor device, the plurality ofsemiconductor chips each have an informational notation specific theretoprovided on a back face thereof (claim 25).

[0070] The specific informational notation preferably includes at leastone informational notation selected from a model designation of thesemiconductor chip, a production lot number of the semiconductor chipand an alignment mark to be utilized for assembling a chip-on-chipstructure by employing the semiconductor chip (claim 26).

[0071] The specific informational notation is preferably represented bya bar code and a two-dimensional code (claim 27).

[0072] The semiconductor chip for the chip-on-chip structure inaccordance with claim 23 is mounted on another semiconductor chip on thebasis of the specific informational notation provided on the back faceof the semiconductor chip for assembling the chip-on-chip structure.

[0073] More specifically, if an alignment mark for recognition of theorientation of the semiconductor chip, the electrode arrangement on thesemiconductor chip or the like is provided as the informationalnotation, the semiconductor chip can easily be positioned with respectto another semiconductor chip on the basis of the alignment mark so asto be mounted on the another chip with the front face thereof downward.

[0074] The specific informational notation may be a human-recognizablenotation, or may be a notation optically detectable by an OCR, or abar-code notation. Alternatively, a plurality of notations may beprovided in different forms in combination.

[0075] When the chip-on-chip structure is to be assembled, propersemiconductor chips are selected from different types of semiconductorchips by reading the specific informational notations, and positioninginformation is obtained by reading the informational notations by anassembling robot.

[0076] After the assembling of the chip-on-chip structure, whether ornot the semiconductor chips have properly been assembled into thechip-on-chip structure can easily be checked on the basis of theinformational notations.

[0077] With the arrangement according to claim 24, whether or notpredetermined semiconductor chips are employed as components of thechip-on-chip semiconductor device can easily be checked by reading thespecific informational notations provided on the respectivesemiconductor chips.

[0078] Further, whether or not the assembled state of the device, e.g.,the orientation, position and the like of each of the semiconductorchips, is proper can be judged on the basis of the specificinformational notations.

[0079] The chip-on-chip semiconductor device is molded and thendelivered to the market and, when a need arises to check makers and thelike of the respective semiconductor chips incorporated in thesemiconductor device, the back faces of the semiconductor chips areexposed from a mold package for checking the specific informationalnotations of the semiconductor chips. Thus, production information onthe semiconductor chips can be checked.

[0080] In accordance with an inventive aspect of claim 28, there isprovided a semiconductor chip for a chip-on-chip structure in which aplurality of semiconductor chips are bonded to one another in aface-to-face stacked relation, the semiconductor chip having apositioning pin hole extending therethrough from a front face to a backface thereof for recognition of an electrode arrangement, an electrodetype and the like from the back side thereof.

[0081] With the arrangement according to claim 28, the positioning pinhole is formed in the semiconductor chip for the chip-on-chip structureas extending therethrough from the front face to the back face thereof.When the chip-on-chip structure is assembled, the predeterminedpositioning of the semiconductor chip can be performed on the basis ofthe positioning pin hole from the back side thereof, so that thesemiconductor chip can easily be positioned on a front face of anothersemiconductor chip with a high level of precision by viewing thesemiconductor chip from the back side thereof.

[0082] Since the positioning can easily be achieved, the time requiredfor the assembling of the chip-on-chip structure can be reducedadvantageously for practical applications.

[0083] Where a plurality of positioning pin holes are formed in thesemiconductor chip, the orientation of the mounted semiconductor chipcan correctly be checked on the basis of the plurality of positioningpin holes.

[0084] In accordance with an inventive aspect of claim 29, there isprovided a chip-on-chip semiconductor device, which comprises a firstsemiconductor chip disposed with a front face thereof upward, and asecond semiconductor chip bonded to the first semiconductor chip with afront face thereof facing downward as opposed to the front face of thefirst semiconductor chip, wherein the second semiconductor chip has apositioning pin hole extending therethrough from the front face to aback face thereof so that the first and second semiconductor chips arepositioned with respect to each other on the basis of the positioningpin hole.

[0085] With this arrangement, the first and second semiconductor chipsbonded to each other in a properly positioned state can be incorporatedin the chip-on-chip semiconductor device.

[0086] In accordance with an inventive aspect of claim 30, there isprovided a chip-on-chip mounting method, which comprises the steps of:placing a first semiconductor chip with a front face thereof upward; andpositioning a second semiconductor chip having a positioning pin holeaccording to claim 1 with respect to the first semiconductor chip on thebasis of a positioning pin hole formed in the second semiconductor chipto bond the first and second semiconductor chips to each other in astacked relation with a front face of the second semiconductor chip keptin a predetermined positional relation with the front face of the firstsemiconductor chip.

[0087] This arrangement provides a practical mounting method for achip-on-chip semiconductor device. That is, the chip-on-chip mountingmethod can be employed for practical applications on a production lineand the like, and the chip-on-chip structure can be assembled in ashorter time.

[0088] Embodiments of the present invention will hereinafter bedescribed with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0089]FIG. 1A is a schematic plan view of a semiconductor wafer, andFIG. 1B is a schematic plan view illustrating a positional relationshipbetween an electrode arrangement and profiles of a relatively largesemiconductor chip and a relatively small semiconductor chip which arediced from the semiconductor wafer;

[0090]FIG. 2A is a schematic vertical sectional view of a semiconductorchip for chip-on-chip mounting in accordance with one embodiment of thepresent invention, and FIGS. 2B and 2C are a schematic plan view and aschematic bottom view, respectively, of the semiconductor chip;

[0091]FIG. 3 is a schematic bottom view of a semiconductor chipaccording to another embodiment of the invention;

[0092]FIG. 4A is a schematic vertical sectional view of a chip-on-chipsemiconductor device according to further another embodiment of theinvention, and FIG. 4B is a schematic plan view of the semiconductordevice;

[0093]FIG. 5 is a schematic vertical sectional view illustrating theconstruction of a chip-on-chip semiconductor device employing asemiconductor chip for chip-on-chip mounting in accordance with stillanother embodiment of the invention;

[0094]FIG. 6 is a schematic plan view of a primary semiconductor chipfor chip-on-chip mounting in accordance with further another embodimentof the invention;

[0095]FIG. 7 is a schematic vertical sectional view illustrating theconstruction of a chip-on-chip semiconductor device according to stillanother embodiment of the invention;

[0096]FIG. 8 is a schematic plan view of the chip-on-chip semiconductordevice shown in FIG. 7;

[0097]FIGS. 9A to 9C are diagrams illustrating exemplary back marksprovided on a back face of a secondary chip;

[0098]FIG. 10 is a diagram illustrating back marks provided on a backface of a primary chip;

[0099]FIG. 11 is a schematic vertical sectional view illustrating theconstruction of a chip-on-chip semiconductor device according to furtheranother embodiment of the invention;

[0100]FIG. 12 is a schematic bottom view of the semiconductor deviceshown in FIG. 11;

[0101]FIGS. 13A to 13C are schematic plan views for explaining backmarks according to still another embodiment of the invention;

[0102]FIGS. 14A to 14C are schematic diagrams illustrating exemplarychip-on-chip structures;

[0103]FIG. 15 is a schematic bottom view of a semiconductor chip forchip-on-chip mounting in accordance with further another embodiment ofthe invention;

[0104]FIGS. 16A to 16C are a plan view, a vertical sectional view and abottom view, respectively, which schematically illustrate a chip-on-chipsemiconductor device according to still another embodiment of theinvention;

[0105]FIG. 17 is a schematic vertical sectional view illustrating theconstruction of a chip-on-chip semiconductor device according to furtheranother embodiment of the invention;

[0106]FIG. 18 is a schematic plan view of the chip-on-chip semiconductordevice shown in FIG. 17; and

[0107]FIG. 19 is a fragmentary enlarged schematic plan view forexplaining a positional relationship between electrodes and apositioning pin hole 28 provided on a secondary chip 2 according tostill another embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0108] First, an explanation will briefly be given to a reason whyelectrodes provided on a semiconductor chip are not always arranged in apredetermined positional relationship with respect to the profile of thesemiconductor chip but the positional relationship tends to vary.

[0109]FIG. 1A is a schematic plan view of a semiconductor wafer 10. Anintegrated circuit and the like are formed in each predefined area ofthe semiconductor wafer 10. The semiconductor wafer 10 is diced (or cut)along scribe lines 9 into a plurality of separate semiconductor chips bymeans of a dicing saw.

[0110] The semiconductor chips thus cut out tend to have differentexterior sizes due to slight misalignment of the dicing saw with respectto each scribe line 9 which occurs when the semiconductor wafer 10 iscut along the scribe line 9. As a result, a semiconductor chip 1A havinga larger plan (exterior) size and a semiconductor chip 1B having asmaller plan size are produced as shown in FIG. 1B. The semiconductorchips, which have different exterior sizes, each equally have theintegrated circuit and electrodes 8 provided on a front face thereof. Inthe semiconductor chip 1B of a smaller exterior size, the electrodes 8are located relatively close to the periphery thereof. In thesemiconductor chip 1A of a larger exterior size, on the other hand, theelectrodes 8 are located relatively inwardly of the periphery thereof.Thus, the electrodes 8 are not always located in the same positionalrelationship with respect to the profile of each semiconductor chip, sothat the aforesaid problem is encountered which is to be solved by thepresent invention.

[0111]FIGS. 2A to 2C illustrate the construction of a semiconductor chip3 for chip-on-chip mounting in accordance with one embodiment of thepresent invention. Particularly, FIGS. 2A, 2B and 2C are a schematicvertical sectional view, a schematic plan view and a schematic bottomview, respectively, of the semiconductor chip. The semiconductor chip 3is composed of a semiconductor such as silicon, GaAs or Ge. Thesemiconductor chip 3 for chip-on-chip mounting has an active region 32provided in a front face 31 thereof, in which an integrated circuit andthe like have been formed. A plurality of electrodes 33 are provided ina predetermined arrangement on the front face 31.

[0112] A plurality of electrode marks 35 are provided on a back face 34of the semiconductor chip 3 in association with the electrodes 33provided on the front face 31. This is a feature of this embodiment.

[0113] The plurality of electrode marks 35 are disposed in the samearrangement as the electrode arrangement and correspond to therespective electrodes 33. Accordingly, the arrangement of the electrodemarks 35 represents the arrangement of the electrodes 33 provided on thefront face 31 when viewed from the side of the back face 34 of thesemiconductor chip 3.

[0114] Therefore, when the semiconductor chip 3 is mounted on anothersemiconductor chip with the front face 31 thereof facing downward asopposed to a front face of the another semiconductor chip, thesemiconductor chip 3 can be positioned with respect to the anothersemiconductor chip on the basis of the electrode marks 35. As a result,the semiconductor chips can be bonded to each other with almost nooffset between the opposed electrodes thereof.

[0115]FIG. 3 is a schematic bottom view of a semiconductor chip 4according to another embodiment of the invention. In the semiconductorchip 4 shown in FIG. 3, electrode marks 35 are provided on a back face34 thereof in association with predetermined ones of electrodes 33provided on a front face thereof. More specifically, four electrodemarks 35 are provided on the back face 34 of the semiconductor chip 4,for example, in association with electrodes provided in four corners ofthe semiconductor chip 4. In FIG. 3, the other electrodes on the frontface are denoted in broken lines by reference numeral 33, and noelectrode mark is provided for those electrodes 33. In this embodiment,the arrangement of the electrodes can be checked from the side of theback face 34 by way of the electrode marks 35 provided in the fourcorners in association of the corner electrodes. Therefore, thesemiconductor chip 4 can easily be positioned with respect to anothersemiconductor chip with its face down for formation of the chip-on-chipstructure, like the semiconductor chip 3 described with reference toFIGS. 2A to 2C.

[0116] The provision of the four electrode marks 35 in association withthe four corner electrodes is merely illustrative, and the number andarrangement of the electrode marks 35 to be provided may be determinedas desired.

[0117] The electrode marks 35 on the semiconductor chip 3 or 4 areformed on a wafer before the wafer is diced for production of thesemiconductor chip 3 or 4. The electrode marks 35 may be formed, forexample, by a printing process or a laser process. Alternatively, a dualside aligner may be employed when the electrodes and bumps are formed onthe front face through light exposure, so that the electrode marks 1 areformed on the back face through light exposure simultaneously with theformation of the electrodes and the like on the front face in aproduction process.

[0118]FIG. 4A is a schematic vertical sectional view of a chip-on-chipsemiconductor device according to further another embodiment of theinvention, and FIG. 4B is a schematic plan view of the semiconductordevice.

[0119] Referring to FIGS. 4A and 4B, the chip-on-chip semiconductordevice includes a primary chip (or mother chip) 1 and a secondary chip(or daughter chip) 2 which are disposed in a double-stacked relation.The primary chip 1 and the secondary chip 2 are semiconductor chips suchas of silicon, GaAs or Ge. In this embodiment, the primary chip 1 andthe secondary chip 2 are silicon chips, but any types of semiconductorchips may be employed in combination. For example, the primary chip 1and the secondary chip 2 may be composed of silicon and GaAs,respectively, or may be composed of semiconductors in any othercombination.

[0120] The primary chip 1 and the secondary chip 2 are bonded to eachother with a front face 11 of the primary chip opposed to a front face21 of the secondary chip 2. The primary chip 1 has an active region 12provided in the front face thereof, in which an integrated circuit andthe like have been formed. Similarly, the secondary chip 2 has an activeregion 22 provided in the front face 21 thereof, in which an integratedcircuit and the like have been formed. The stacked primary and secondarychips 1, 2 are bonded to each other via bumps which respectively connectelectrodes 13 provided on the front face 11 of the primary chip toelectrodes 23 provided on the front face 22 of the secondary chip.

[0121] For assembling of the chip-on-chip semiconductor device, theprimary chip 1 is first placed with the front face 11 thereof upward,and then the secondary chip 2 is positioned with respect to the primarychip 1 with the front face 21 of the secondary chip 2 facing downward.At this time, the positions of the electrodes provided on the front faceof the secondary chip 2 can be checked by way of electrode marks 25provided on a back face 24 of the secondary chip 2. Therefore, thesecondary chip 2 can properly be positioned with respect to the primarychip 1 on the basis of the electrode marks 25. As a result, theelectrodes 13 on the primary chip 1 can respectively be connected to theelectrodes 23 on the secondary chip 2 via the bumps with almost nooffset.

[0122] In the chip-on-chip semiconductor device shown in FIGS. 4A and4B, the electrode marks 25 are provided on the back face 24 of thesecondary chip 2. Therefore, it can be checked whether or not theelectrodes of the secondary chip 2 are offset from the correspondingelectrodes and circuit arrangement on the front face 11 of the primarychip 1 in the assembled chip-on-chip semiconductor device.

[0123] From another viewpoint, it can be checked at a glance whether ornot the chip-on-chip semiconductor device is produced by employing theaforesaid semiconductor chip 3 or 4 for chip-on-chip mounting providedwith the electrode marks 35.

[0124]FIG. 5 is a schematic vertical sectional view illustrating theconstruction of a chip-on-chip semiconductor device produced byemploying semiconductor chips for chip-on-chip mounting in combinationin accordance with still another embodiment of the invention. Thesemiconductor device includes a primary chip 1 and two secondary chips2A, 2B. The primary chip 1 and the two secondary chips (second chip andthird chip) 2A, 2B are semiconductor chips such as of silicon (Si),gallium arsenide (GaAs) or germanium (Ge). The primary chip 1 and thetwo secondary chips 2A, 2B are preferably composed of the samesemiconductor, e.g., silicon, but the semiconductor material therefor isnot limited thereto. For example, the primary chip 1 and the secondarychips 2A, 2B may be composed of silicon and gallium arsenide,respectively, or may be composed of semiconductors in any othercombination.

[0125] The primary chip 1 is bonded to the secondary chips 2A, 2B in astacked relation with a front face 11 of the primary chip 1 opposed tofront faces 21 of the secondary chips 2A, 2B. The primary chip 1 has anactive region 12 provided in the front face 11 thereof, in which anintegrated circuit and the like have been formed. Similarly, thesecondary chips 2A, 2B each have an active region 22 provided in thefront face 21 thereof, in which an integrated circuit and the like havebeen formed. The primary chip 1 is bonded to the secondary chips 2A, 2Bthus stacked via bumps which respectively connect electrodes 13A, 13Bprovided on the front face 11 of the primary chip to electrodes 23A, 23Bprovided on the front faces 21 of the secondary chips.

[0126] In FIG. 5, a reference numeral 14 denotes a back face of theprimary chip 1, and a reference numeral 24 denotes back faces of thesecondary chips 2A, 2B.

[0127]FIG. 6 is a schematic plan view of the primary chip 1 of thechip-on-chip semiconductor device shown in FIG. 5, wherein the positionsof the stacked secondary chips 2A, 2B are indicated by broken lines.

[0128] A feature of the primary chip 1 in this embodiment is thatpositioning reference marks 90 a, 90 b are provided on the front face 11thereof for the positioning of the secondary chips 2A, 2B.

[0129] One 90 a of the positioning reference marks serves as a referencepoint for positioning the secondary chip 2A on the front face 11 of theprimary chip 1 for mounting thereof. The secondary chip 2A is positionedon the front face 11 of the primary chip 1 with the front face thereofdownward. By the positioning on the basis of the positioning referencemark 90 a, the secondary chip 2A can properly be disposed in apredetermined stacked relation with the primary chip. The positioningreference mark 90 a is provided in a predetermined positionalrelationship with the electrodes 13A to be connected to the secondarychip 2A. Therefore, the positioning of the secondary chip 2A can beachieved with a higher level of precision than in a case where thepositioning of the secondary chip 2A is achieved by determining thecoordinates of the secondary chip 2A on the basis of a relationshipbetween the profiles of the primary chip 1 and the secondary chip 2A.

[0130] Similarly, the mounting of the secondary chip 2B is achieved bypositioning the secondary chip 2B on the basis of the positioningreference mark 90 b.

[0131] In this embodiment, the positioning reference mark 90 a for thesecondary chip 2A and the positioning reference mark 90 b for thesecondary chip 2B have different shapes. Therefore, it is easy toidentify the positioning reference marks 90 a, 90 b by image processingor the like. On the basis of the result of the image processing, thesecondary chips 2A, 2B can be located in predetermined positions on theprimary chip.

[0132] The positioning reference marks 90 a and 90 b can respectively beprovided in any desired positions having predetermined positionalrelationships with the electrodes 13A and 13B. The front face 11 of theprimary chip 1 except for the electrodes is generally covered with apassivation film, so that the marks 90 a, 90 b can be provided in anydesired positions on the passivation film.

[0133] Formation of the marks 90 a, 90 b may be achieved, for example,by a printing process or a laser process. Alternatively, the marks maybe formed in association with the electrode positions by employing analigner for light exposure of an integrated circuit pattern in theactive region in a production process.

[0134] By thus providing the positioning reference marks 90 a, 90 b, themounting positions of the secondary chips 2A, 2B can clearly be definedfor proper positioning of the secondary chips 2A, 2B when the secondarychips 2A, 2B are mounted on the front face 11 of the primary chip 1. Asa result, electrical connection between the electrodes 13A of theprimary chip 1 and the electrodes 23A of the secondary chip 2A andbetween the electrodes 13B of the primary chip 1 and the electrodes 23Bof the secondary chip 2B can assuredly be established.

[0135] The positions and shapes of the positioning reference marks 90 a,90 b provided on the primary chip 1 in the aforesaid embodiment aremerely illustrative, and various modifications may be made thereto. Forexample, the mark 90 a may be located in a position which allows forregistration with an edge of the secondary chip 2A. Alternatively, aplurality of marks 90 a may be provided on the primary chip so that thepositioning of the secondary chip 2A can be based on the plurality ofmarks 90 a.

[0136]FIG. 7 is a schematic vertical sectional view illustrating theconstruction of a chip-on-chip semiconductor device according to stillanother embodiment of the invention. The semiconductor device includes aprimary chip 1 and a secondary chip 2. The primary chip 1 and thesecondary chip 2 are semiconductor chips such as of silicon, galliumarsenide (GaAs) or germanium (Ge). The primary chip 1 and the secondarychip 2 are preferably composed of the same semiconductor, e.g., silicon,but the semiconductor material therefor is not limited thereto. Forexample, the primary chip 1 and the secondary chip 2 may be composed ofsilicon and GaAs, respectively, or may be composed of semiconductors inany other combination.

[0137] The primary chip 1 and the secondary chip 2 are bonded to eachother with a front face 11 of the primary chip 1 opposed to a front face21 of the secondary chip 2. The primary chip 1 has an active region 12provided in the front face 11 thereof, in which an integrated circuitand the like have been formed. Similarly, the secondary chip 2 has anactive region 22 provided in the front face 21 thereof, in which anintegrated circuit and the like have been formed. The stacked primaryand secondary chips 1, 2 are bonded to each other with electrodes 13 onthe front face 11 respectively connected to electrodes 23 on the frontface 21.

[0138] In FIG. 7, a reference numeral 14 denotes a back face of theprimary chip 1, and a reference numeral 24 denotes a back face of thesecondary chip 2.

[0139]FIG. 8 is a schematic plan view of the chip-on-chip semiconductordevice. A feature of this embodiment is that a back mark 250 is providedon the back face 24 of the secondary chip 2. The back mark 250 allowsfor recognition of the orientation of the secondary chip 2, thearrangement of the electrodes 23 provided on the front face 21 of thesecondary chip 2, and the like. When the primary chip 1 is placed withthe front face 11 thereof upward and the secondary chip 2 is positionedwith respect to the primary chip 1 with the front face thereof downward,the positioning of the secondary chip 2 can be achieved on the basis ofthe back mark 250. More specifically, the orientation of the secondarychip 2 can be recognized by way of the back mark 250, so that there isno possibility that the secondary chip 2 is mounted on the primary chip1 with a 180-degree angular offset. If the back mark 250 has a specificpositional relationship with any of the electrodes 23 (see FIG. 1)provided on the front face 21 of the secondary chip 2, e.g., if apredetermined electrode 23 is located on a vertical line extendingthrough the back mark 250, the electrode arrangement on the secondarychip 2 can be recognized on the basis of the back mark 250.

[0140] Though not shown in FIG. 8, the circuit arrangement and theelectrodes are provided on the front face 11 (active region) of theprimary chip 1 in a recognizable manner. Therefore, the back mark 250 onthe back face 24 of the secondary chip 2 is properly positioned withrespect to the circuit arrangement and the electrodes on the front face11 of the primary chip 1 when the secondary chip 2 is mounted on theprimary chip 1.

[0141] Since the back mark 250 is thus provided on the back face 24 ofthe secondary chip 2, the positioning of the secondary chip 2 can easilybe achieved on the basis of the back mark 250.

[0142]FIGS. 9A to 9D are diagrams illustrating examples of the back mark250 provided on the back face 24 of the secondary chip 2. Although thesingle back mark 250 is provided in FIG. 8, a plurality of back marksmay be provided.

[0143]FIG. 9A illustrates three back marks 250 provided in three cornersof the back face 24.

[0144] As shown in FIG. 9A, the back marks 250 are each represented by“·” (point or circle), but may each be represented by “L” (hook- orL-shape), “+”, “−” or the like.

[0145] Alternatively, the back marks 250 may each be represented by aline which extends along an edge of the secondary chip 2 as shown inFIG. 9C.

[0146] Further, the back marks 250 may be represented by crossed linesas shown in FIG. 9D. Besides those shown in FIGS. 8 and 9A to 9D, anynotations and marks such as characters and symbols may be employed asthe back marks 250.

[0147] The back face 24 of the secondary chip 2 is generally amirror-like surface, so that the arrangement of the electrodes providedon the front face of the secondary chip 2 cannot be recognized from theside of the back face 24. This is why the back marks 250 are provided onthe back face 24 for recognition of the orientation and electrodearrangement of the secondary chip 2.

[0148] The back marks 250 are formed on a wafer before the wafer isdiced for production of the secondary chip 2. The formation of the backmarks 250 may be achieved by a printing process or a laser process.Alternatively, the marks may be formed in association with the electrodepositions by employing a dual-side aligner as an aligner for lightexposure of an integrated circuit pattern in the active region in aproduction process.

[0149] Although the foregoing explanation is directed to a case wherethe back marks 250 are provided on the back face 24 of the secondarychip 2, back marks may be provided on the primary chip 1. Morespecifically, back marks 15 may be provided on the back face 14 of theprimary chip 1 as shown in FIG. 10. Where the secondary chip 2 ismounted on the front face 11 of the primary chip 1 for production of thechip-on-chip semiconductor device, the positioning of the secondary chip2 can be controlled on the basis of the back marks 15 provided on theback face 14 of the primary chip 1. The back marks 15 on the primarychip 1 is effective for such an application.

[0150] The back marks 15 on the primary chip 1 are not limited to thoseillustrated in FIG. 10, but may have any of various shapes and formslike the back marks 250 on the secondary chip 2 illustrated in FIGS. 8and 9A to 9D.

[0151] In the assembled chip-on-chip semiconductor device, the backmarks 250 may be provided only on the secondary chip 2, or the backmarks 15 may be provided only on the primary chip 1. Alternatively, theback marks 15 and 250 may be provided on the primary chip 1 and thesecondary chip 2, respectively.

[0152]FIG. 11 is a schematic vertical sectional view illustrating theconstruction of a chip-on-chip semiconductor device according to furtheranother embodiment of the invention. In this semiconductor device, alead frame 30 is attached to a back face 14 of a primary chip 1. Thelead frame 30 is bonded onto the back face 14 of the primary chip 1 byan adhesive 311.

[0153]FIG. 12 is a schematic bottom view of the semiconductor device ofFIG. 11. In this embodiment, back marks 330 are provided on a back face321 of the lead frame 30. The back marks 330 may have any desired shape,like the back marks on the secondary chip 2 and the primary chip 1. Theprovision of the back marks 330 on the lead frame 30 offers thefollowing advantages:

[0154] (i) Where the lead frame 30 is attached to the primary chip 1,the lead frame 30 can properly be fitted on a predetermined portion ofthe back face of the primary chip 1 on the basis of the back marks 330of the lead frame 30 and the back marks 15 on the primary chip 1.

[0155] (ii) There is a possibility that the back marks 15 on the backface 14 of the primary chip 1 are hidden by the attached lead frame 30.In such a case, the positioning of the primary chip 1 can be achieved onthe basis of the back marks 330 on the lead frame 30, or the positioningof the secondary chip 2 can be achieved on the basis of the back marks330.

[0156] (iii) By attaching the lead frame 30 to the primary chip 1provided with no back mark, the positioning of the primary chip 1 can beachieved on the basis of the back marks 330 on the lead frame 30, or thepositioning of the secondary chip 2 can be achieved on the basis of theback marks 330.

[0157] In FIG. 12, comb-shaped portions provided on the right and leftsides of the primary chip 1 are cut along one-dot-and-dash lines andlater serve as electrodes.

[0158]FIGS. 13A to 13C are schematic plan views for explaining backmarks according to still another embodiment of the invention. As shownin FIG. 13A, back marks 250 are provided on a back face 24 of asecondary chip 2 as extending from edges of the secondary chip 2.Although the four back marks 250 are illustrated, only one back mark maybe provided. On the other hand, front marks 16 are provided on a frontface 11 of a primary chip 1 as shown in FIG. 13B. The front marks 16 areprovided so as to be brought into a predetermined positionalrelationship with the back marks 250 on the secondary chip 2. Morespecifically, the back marks 250 and the front marks 16 form tally marksto be paired with each other as shown in FIG. 13C when the secondarychip 2 is mounted on the primary chip 1. Thus, the primary chip 1 canproperly be positioned with respect to the secondary chip 2 when thesecondary chip 2 is to be mounted on the primary chip 1.

[0159] Since the formation of the marks on the back face 24 of thesecondary chip 2 can be achieved without any trouble, the back marks canbe provided in any desired positions on the back face 24. On the otherhand, an integrated circuit and the like are provided in the front face11 of the primary chip 1, but covered with a passivation film.Therefore, the front marks 16 can be provided in any desired positionson the passivation film because the front face 11 of the primary chip 1except for the electrodes is covered with the passivation film. Thus,the tally marks can be provided as described above.

[0160]FIGS. 14A to 14C are schematic diagrams illustrating examples ofthe chip-on-chip structure. The chip-on-chip structure maybe such thatone secondary chip 2 is mounted on one primary chip 1 as described inthe foregoing embodiments, or may be such that two or more secondarychips 2 are mounted on one primary chip 1 as shown in FIGS. 14A and 14B.

[0161] Further, the chip-on-chip structure may be such that a primarychip 1 and a secondary chip 2 having substantially the same size arestacked one on the other as shown in FIG. 14C. For production of any ofsuch chip-on-chip structures, the back marks are utilized to properlyposition the semiconductor chips with respect to each other.

[0162]FIG. 15 is a schematic bottom view of a semiconductor chip 5 forchip-on-chip mounting in accordance with further another embodiment ofthe invention. The semiconductor chip 5 for chip-on-chip mounting iscomposed of a semiconductor such as silicon, GaAs or Ge. Thesemiconductor chip 5 has notations, such as the model designation of thesemiconductor chip 5 (e.g., “BU 00XX”), the production lot number of thesemiconductor chip (e.g., “S-0001”), a bar code indicative of the modeldesignation and the production lot number, and an alignment mark 55,which are provided on a back face 54 of the semiconductor chip 5. Thisis a feature of this embodiment.

[0163] In general, back faces of conventional semiconductor chips aremirror-like surfaces, on which no notation is provided. When achip-on-chip semiconductor device is assembled by employing such asemiconductor chip, mounting conditions should manually be inputted foreach type of semiconductor chips into an assembling apparatus. Themanual input of the mounting conditions may lead to erroneous input.

[0164] In this embodiment, informational notations specific to thesemiconductor chip 5, for example, notations for information on mountingconditions and semiconductor device production and alignment marks 55for alignment (positioning) of the semiconductor chip for the mountingthereof, are provided on the back face 54 of the semiconductor chip 5.The informational notations specific to the semiconductor chip 5 may berepresented by human-readable characters and symbols or by an opticallyreadable bar code or two-dimensional code. The human-readable notationsand the optically readable notations may be provided in combination.

[0165] The chip-specific informational notations provided on the backface 54 of the semiconductor chip 5 are to be read by a reader of theassembling apparatus when the chip-on-chip structure is assembled byemploying the semiconductor chip 5. This obviates the need for themanual input of the mounting conditions, and prevents the erroneousinput of the mounting conditions.

[0166] In general, plural types of semiconductor chips are incorporatedin a chip-on-chip structure. When the semiconductor chips are to besequentially assembled to form the chip-on-chip structure by means ofthe assembling apparatus, the plural types of semiconductor chips areidentified on the basis of the specific informational notations providedon back faces 54 of the respective semiconductor chips. This eliminatesa possibility of mounting a wrong semiconductor chip.

[0167] The provision of the specific informational notations on the backface 54 of the semiconductor chip 5 may be achieved by a printingprocess or a laser process. However, it is more preferable that thespecific informational notations are provided on a wafer by using thesame material as a bump material when a bump forming process isperformed for formation of bumps on the front face of the semiconductorchip 5 before the wafer is diced. Examples of the bump material includeAu, Pd, Pt, Ag, Ir (iridium), Ni and Cu, any of which is preferably usedfor the formation of the specific informational notations on the backface 54 of the semiconductor chip 5. The informational notations formedof the oxidation-resistant metal material same as the bump material canbe checked even after a semiconductor device obtained by molding andpost-processing the chip-on-chip structure incorporating thesemiconductor chip is delivered as a product to the market. That is, thespecific informational notations on the back face 54 of thesemiconductor chip 5 can be read by removing a mold package from thesemiconductor device.

[0168]FIGS. 16A, 16B and 16C are a plan view, a vertical sectional viewand a bottom view, respectively, which schematically illustrate achip-on-chip semiconductor device according to still another embodimentof the invention.

[0169] As shown in FIG. 16B, the chip-on-chip semiconductor deviceincludes a primary chip 1 and a secondary chip 2 disposed in a doublestacked relation. The primary chip 1 and the secondary chip 2 aresemiconductor chips such as of silicon, GaAs or Ge. In this embodiment,the primary chip 1 and the secondary chip 2 are each composed ofsilicon, but the material therefor is not limited thereto. For example,the primary chip 1 and the secondary chip 2 may be composed of siliconand GaAs, respectively, or may be composed of semiconductors in anyother combination.

[0170] The primary chip 1 is bonded to the secondary chip 2 in a stackedrelation with a front face 11 of the primary chip 1 opposed to a frontface 21 of the secondary chip 2. The primary chip 1 has an active region12 provided in the front face 11 thereof, in which an integrated circuitand the like have been formed. Similarly, the secondary chip 2 has anactive region 22 provided in the front face 21 thereof, in which anintegrated circuit and the like have been formed. The stacked primaryand secondary chips 1, 2 are bonded to each other via bumps whichrespectively connect electrodes 13 provided on the front face 11 toelectrodes 23 provided on the front face 12.

[0171] For the assembling of the chip-on-chip semiconductor device, theprimary chip 1 is placed, for example, with the front face 11 thereofupward, and then the secondary chip 2 is positioned with respect to theprimary chip 1 with the front face 21 thereof downward. As shown in FIG.16A, informational notations specific to the secondary chip 2 areprovided on a back face 24 of the secondary chip 2. On the basis ofalignment marks 55 of the informational notations, the secondary chip 2can easily be positioned with respect to the primary chip 1.

[0172] As shown in FIG. 16A, the informational notations provided on theback face 24 of the secondary chip 2 include the model designation andproduction lot number of the secondary chip 2, and a bar code indicativeof the model designation and the production lot number, in addition tothe alignment marks 55.

[0173] Similarly, informational notations including the model number andproduction lot number of the primary chip 1, a bar code or a twodimensional code indicative of the model number and the production lotnumber, and alignment marks 151 are provided on a back face 14 of theprimary chip 1.

[0174] Therefore, information on the respective semiconductor chipsincorporated in the chip-on-chip structure of the semiconductor devicecan easily be checked.

[0175] By utilizing the alignment marks 151, 55, the positioning of thesecondary chip 2 with respect to the primary chip 1 can easily beachieved, thereby providing the chip-on-chip semiconductor deviceproperly assembled in a desired state.

[0176] The aforesaid specific informational notations provided on theback faces of the semiconductor chips are merely illustrative, and anyother informational notations may be provided on the back faces. What isimportant is that the notations provide information on the type of thesemiconductor chip, the production process and the like.

[0177] The shape of the alignment marks are not limited to “L” (hook- orL-shape), but may be any desired shape such as “·” (point or circle),“+” or “−”.

[0178] As required, the provision of the alignment marks may beobviated, and the bar code, for example, may be utilized as apositioning reference mark.

[0179]FIG. 17 is a schematic vertical sectional view illustrating theconstruction of a chip-on-chip semiconductor device according to furtheranother embodiment of the invention. The chip-on-chip semiconductordevice includes a primary chip 1 and a secondary chip 2. The primarychip 1 and the secondary chip 2 are semiconductor chips such as ofsilicon, gallium arsenide (GaAs) or germanium (Ge). The primary chip 1and the secondary chip 2 are preferably composed of a semiconductor ofthe same type, e.g., silicon, but the material therefor is not limitedthereto. For example, the primary chip 1 and the secondary chip 2 may becomposed of silicon and GaAs, respectively, or may be composed ofsemiconductors in any other combination.

[0180] The primary chip 1 is bonded to the secondary chip 2 in a stackedrelation with a front face 11 of the primary chip 1 opposed to a frontface 21 of the secondary chip 2. The primary chip 1 has an active region12 provided in the front face 11 thereof, in which an integrated circuitand the like have been formed. Similarly, the secondary chip 2 has anactive region 22 provided in the front face 21 thereof, in which anintegrated circuit and the like have been formed. The stacked primaryand secondary chips 1, 2 are bonded to each other via bumps whichrespectively connect electrodes 13 provided on the front face 11 toelectrodes 23 provided on the front face 12.

[0181] A feature of this embodiment is that positioning pin holes 28 areformed in the secondary chip 2 as extending therethrough from the frontface 21 to a back face 24 thereof. As will be described, the positioningpin holes are utilized for recognition of the orientation of the circuitformed in the active region 22 of the secondary chip 2 and thearrangement of the electrodes on the secondary chip 2 from the side ofthe back face 24 thereof.

[0182] In FIG. 17, a reference numeral 14 denotes a back face of theprimary chip 1.

[0183]FIG. 18 is a schematic plan view of the chip-on-chip semiconductordevice. The circuit arrangement, the electrodes and the like areprovided on the front face 11 (active region) of the primary chip 1 in arecognizable manner. When the secondary chip 2 is to be mounted in apredetermined position on the front face 11 of the primary chip 1, theprimary chip 1 is first positioned, and the circuit arrangement, theelectrodes and the like on the front face 11 are detected. The detectionmay be achieved by capturing an image of the front face 11 of thepositioned primary chip 1, for example, by a CCD camera and processingthe image. The secondary chip 2 is positioned in the predeterminedposition on the front face 11 of the primary chip 1 with the front faceof the secondary chip 2 facing downward.

[0184] However, the type, arrangement and orientation of the electrodesprovided on the front face of the secondary chip 2 cannot be recognizedfrom the side of the back face 24 of the secondary chip 2, because theback face 24 of the secondary chip 2 is generally a mirror-like surface.In this embodiment, the positioning of the secondary chip 2 is based onthe positioning pin holes 28 formed in the secondary chip 2 as extendingtherethrough from the front face 21 to the back face 24 thereof asdescribed above.

[0185] A detailed explanation will be given with reference to FIG. 19.FIG. 19 is a fragmentary enlarged schematic plan view illustrating thesecondary chip 2 as viewed from the side of the front face 21 thereof.In a left upper corner portion defined by an upper edge 2 _(UL) and aleft edge 2 _(LL) on the front face 21 of the secondary chip 2,electrodes 23 ₁, 23 ₂, 23 ₃, . . . are provided from the left to theright along the upper edge 2 _(UL), and electrodes 23 ₁, 23 ₁₁, 23 ₁₂, .. . are provided from the top to the bottom along the left edge 2 _(LL).In this case, the positions of the upper edge 2 _(UL) and the left edge2 _(LL) vary from chip to chip as indicated by a solid line, aone-dot-and-dash line or a two-dot-and-dash line due to a dicing error.

[0186] In this embodiment, the positioning pin hole 28 is formed in apredetermined positional relation with predetermined electrodes, forexample, the electrodes 23 ₁, 23 ₂ and 23 ₁₁ in the corner portion. Thepositioning pin hole 28 extends vertically through the secondary chip 2from the front face 21 to the back face 24 thereof. By positioning thesecondary chip 2 with respect to the positioning pin hole 28, theelectrodes 23 having the predetermined positional relationship with thepositioning pin hole 28 can be positioned as desired.

[0187] The positioning pin hole 28 is formed in a predeterminedpositional relationship with the plural electrodes 23 ₁, 23 ₂ and 23 ₁₁as described above, or with a predetermined single electrode. In thiscase, the positioning pin hole 28 is, of course, formed as extendingthrough a portion of the secondary chip 2 irrelevant to the integratedcircuit and the like formed in the secondary chip 2.

[0188] The formation of the positioning pin holes 28 may be achieved bymeans of a drill having a diameter of several tens microns, ahigh-pressure water drill or a high-power laser beam which is oftenutilized for processing a printed circuit board or the like, or by anetching process.

[0189] The positioning pin holes 28 may be formed in a semiconductorwafer before the wafer is diced, or formed in the secondary chip 2 afterthe wafer is diced. For efficient processing, the positioning pin holes28 are preferably formed in the semiconductor wafer.

[0190] When the secondary chip 2 is to be mounted on the primary chip 1,the secondary chip 2 is positioned with respect to the primary chip 1 onthe basis of the positioning pin hole 28 which can be seen from the sideof the back face 24 of the secondary chip 2, and then bonded to theprimary chip.

[0191] The positions and number of the positioning pin holes 28 formedin the semiconductor chip 2 described above are merely illustrative, andwhat is important is that the secondary chip 2 is formed with thepositioning pin hole 28 which is utilized for positioning the secondarychip with respect to the primary chip when the secondary chip 2 as asecond chip is to be mounted on the primary chip 1 as a first chip forformation of the chip-on-chip structure.

[0192] It should be understood that the present invention is not limitedto the embodiments described above but various modifications may be madewithin the spirit and scope of the invention as defined by the appendedclaims.

What is claimed is:
 1. A semiconductor chip for a chip-on-chip structurein which a plurality of semiconductor chips are bonded to one another ina stacked relation with electrode-carrying front faces thereof opposedto each other, the semiconductor chip comprising: an electrode markprovided on a back face thereof in association with an electrodeprovided on a front face thereof.
 2. A semiconductor chip for achip-on-chip structure as set forth in claim 1, wherein a plurality ofelectrodes are provided in a predetermined arrangement on the front faceof the semiconductor chip, wherein a plurality of electrode marks areprovided on the back face of the semiconductor chip in association withthe respective electrodes in the same arrangement as the electrodearrangement.
 3. A semiconductor chip for a chip-on-chip structure as setforth in claim 1, wherein a plurality of electrodes are provided in apredetermined arrangement on the front face of the semiconductor chip,wherein electrode marks are provided on the back face of thesemiconductor chip in association with predetermined ones of theplurality of electrodes.
 4. A chip-on-chip semiconductor devicecomprising a plurality of semiconductor chips bonded to one another in astacked relation with electrode-carrying front faces thereof opposed toeach other via electrodes provided on the opposed front faces, whereinelectrode marks are provided on a back face of at least one of thestacked semiconductor chips in association with the electrodes on thefront face of the one semiconductor chip.
 5. A chip-on-chip mountingmethod for stacking first and second semiconductor chips each havingelectrodes provided on a front face thereof so that the electrodes onthe first semiconductor chip are bonded to the electrodes on the secondsemiconductor chip, the method comprising the steps of: placing thefirst semiconductor chip with the front face thereof upward; andpositioning the second semiconductor chip with respect to the firstsemiconductor chip on the basis of electrode marks provided on a backface of the second semiconductor chip in association with the electrodesprovided on the front face of the second semiconductor chip to mount thesecond semiconductor chip on the first semiconductor chip with the frontface of the second semiconductor chip facing downward as opposed to thefront face of the first semiconductor chip.
 6. A primary semiconductorchip serving as a base to be mounted with a secondary semiconductor chipwith a front face thereof bonded to the secondary semiconductor chip,the primary semiconductor chip comprising: a mark provided on the frontface thereof to be utilized as a positioning reference mark when theprimary and secondary semiconductor chips are to be stacked.
 7. Aprimary semiconductor chip as set forth in claim 6, wherein a pluralityof secondary semiconductor chips are to be mounted on the front face ofthe primary semiconductor chip, wherein different positioning referencemarks are provided on the front face of the primary semiconductor chipin association with chip mounting positions in which the respectivesecondary semiconductor chips are to be mounted.
 8. A method formounting a secondary semiconductor chip on a front face of a primarysemiconductor chip serving as a base, the method comprising the stepsof: providing on the front face of the primary semiconductor chip a markwhich serves as a positioning reference mark when the primary andsecondary semiconductor chips are to be stacked; and positioning thesecondary semiconductor chip on the front face of the primarysemiconductor chip on the basis of the positioning reference mark.
 9. Asemiconductor chip for a chip-on-chip structure in which a plurality ofsemiconductor chips are bonded to one another in a face-to-face stackedrelation, the semiconductor chip comprising: a back mark provided on aback face thereof for recognition of orientation thereof and electrodearrangement thereon.
 10. A semiconductor chip for a chip-on-chipstructure as set forth in claim 9, wherein the back mark includes atleast two back marks.
 11. A semiconductor chip for a chip-on-chipstructure as set forth in claim 9, wherein the back mark includes atally mark which is to be brought into a predetermined positionalrelationship with a front mark provided on a front face of anothersemiconductor chip to be bonded to the semiconductor chip in a stackedrelation.
 12. A semiconductor chip for a chip-on-chip structure as setforth in claim 9, where in one of the plurality of semiconductor chipsis a primary chip to be disposed with the front face thereof upward,wherein another of the plurality of semiconductor chips is a secondarychip to be bonded onto the primary chip with the front face thereoffacing downward as opposed to the front face of the primary chip,wherein the back mark is provided on the secondary chip.
 13. Asemiconductor chip for a chip-on-chip structure as set forth in claim 9,where in one of the plurality of semiconductor chips is a primary chipto be disposed with the front face thereof upward, wherein another ofthe plurality of semiconductor chips is a secondary chip to be bondedonto the primary chip with the front face thereof facing downward asopposed to the front face of the primary chip, wherein the back mark isprovided on the primary chip.
 14. A semiconductor chip for achip-on-chip structure as set forth in claim 9, wherein one of theplurality of semiconductor chips is a primary chip to be disposed withthe front face thereof upward, wherein another of the plurality ofsemiconductor chips is a secondary chip to be bonded onto the primarychip with the front face thereof facing downward as opposed to the frontface of the primary chip, wherein the primary chip and the secondarychip are each provided with the back mark.
 15. A semiconductor chip fora chip-on-chip structure as set forth in claim 11, where in one of theplurality of semiconductor chips is a primary chip to be disposed withthe front face thereof upward, wherein another of the plurality ofsemiconductor chips is a secondary chip to be bonded onto the primarychip with the front face thereof facing downward as opposed to the frontface of the primary chip, wherein the front mark is provided on thefront face of the primary chip, and the back mark is provided on thesecondary chip in a predetermined positional relationship with the frontmark on the primary chip.
 16. A semiconductor chip for a chip-on-chipstructure as set forth in claim 12, wherein a lead frame is fitted onthe back face of the primary chip, and the back mark is provided in apredetermined position on the lead frame.
 17. A chip-on-chipsemiconductor device comprising: a first semiconductor chip disposedwith a front face thereof upward; and a second semiconductor chip bondedto the first semiconductor chip with a front face thereof facingdownward as opposed to the front face of the first semiconductor chip,wherein a back mark is provided on a back face of the secondsemiconductor chip so that the first and second semiconductor chips arepositioned with respect to each other on the basis of the back mark. 18.A chip-on-chip semiconductor device as set forth in claim 17, whereinthe back mark includes at least two back marks.
 19. A chip-on-chipsemiconductor device as set forth in claim 17, wherein a front mark isprovided on the front face of the first semiconductor chip in apredetermined positional relationship with the back mark, wherein thefirst and second semiconductor chips have been positioned with respectto each other by bringing the back mark and the front mark into thepredetermined positional relationship.
 20. A chip-on-chip mountingmethod comprising the steps of: placing a first semiconductor chip witha front face thereof upward; and positioning a second semiconductor chipwith respect to the first semiconductor chip on the basis of a back markprovided on the second semiconductor chip to bond the first and secondsemiconductor chips to each other in a stacked relation with a frontface of the second semiconductor chip kept in a predetermined relationwith the front face of the first semiconductor chip.
 21. A chip-on-chipmounting method comprising the steps of: placing a first semiconductorchip having a back mark provided on a back face thereof with a frontface thereof upward; and positioning a second semiconductor chip withrespect to the first semiconductor chip on the basis of the back markprovided on the first semiconductor chip to bond the first and secondsemiconductor chips to each other in a stacked relation with a frontface of the second semiconductor chip kept in a predetermined relationwith the front face of the first semiconductor chip.
 22. A chip-on-chipmounting method as set forth in claim 20, wherein a front mark to bebrought into a predetermined positional relationship with the back markprovided on the second or first semiconductor chip is provided on thefront face of the first or second semiconductor chip not provided withthe back mark, wherein the positioning is achieved by bringing the backmark and the front mark into the predetermined positional relationship.23. A semiconductor chip to be employed for assembling a chip-on-chipstructure in which semiconductor chips are bonded to each other in aface-to-face stacked relation, the semiconductor chip comprising: aninformational notation specific thereto provided on a back face thereofto be utilized at least when the chip-on-chip structure is assembled.24. A chip-on-chip semiconductor device comprising a plurality ofsemiconductor chips bonded to one another in a face-to-face stackedrelation, wherein at least one of the stacked semiconductor chips has aninformational notation specific thereto provided on a back face thereof.25. A chip-on-chip semiconductor device as set forth in claim 24,wherein the plurality of semiconductor chips each have an informationalnotation specific thereto provided on a back face thereof.
 26. Asemiconductor chip as set forth in claim 1 or a semiconductor device asset forth in claim 24, wherein the specific informational notationincludes at least one informational notation selected from a modeldesignation of the semiconductor chip, a production lot number of thesemiconductor chip and an alignment mark to be utilized for assemblingthe chip-on-chip structure by employing the semiconductor chip.
 27. Asemiconductor chip as set forth in claim 23 or a chip-on-chipsemiconductor device, wherein the specific informational notation isrepresented by a bar code.
 28. A semiconductor chip for a chip-on-chipstructure in which a plurality of semiconductor chips are bonded to oneanother in a face-to-face stacked relation, the semiconductor chipcomprising: a positioning pin hole extending therethrough from a frontface to a back face thereof for recognition of an electrode arrangementand an electrode type from the back side thereof.
 29. A chip-on-chipsemiconductor device comprising: a first semiconductor chip disposedwith a front face thereof upward; and a second semiconductor chip bondedto the first semiconductor chip with a front face thereof facingdownward as opposed to the front face of the first semiconductor chip;wherein the second semiconductor chip has a positioning pin holeextending therethrough from the front face to a back face thereof sothat the first and second semiconductor chips are positioned withrespect to each other on the basis of the positioning pin hole.
 30. Achip-on-chip mounting method comprising the steps of: placing a firstsemiconductor chip with a front face thereof upward; and positioning asecond semiconductor chip having a positioning pin hole according toclaim 1 with respect to the first semiconductor chip on the basis of apositioning pin hole formed in the second semiconductor chip to bond thefirst and second semiconductor chips to each other in a stacked relationwith a front face of the second semiconductor chip kept in apredetermined positional relation with the front face of the firstsemiconductor chip.